Through-Silicon Vias for 3D Integration

Through-Silicon Vias for 3D Integration

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<h4><p class="MsoNormal"><span style="font-size:12.0pt;line-height:107%;font-family:"Times New Roman",serif">Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality, <span style="white-space:pre"></span>authenticity, or access to any online entitlements included with the product.<o:p></o:p></span></p></h4><h4><br></h4><h4>A comprehensive guide to TSV and other enabling technologies for 3D integration</h4><p>Written by an expert with more than 30 years of experience in the electronics industry, <i>Through-Silicon Vias for 3D Integration</i> provides cutting-edgeinformation on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies. Applications to highperformance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed.</p><p>This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems.</p><p>Coverage includes:</p><ul><li>Nanotechnology and 3D integration for the semiconductor industry</li><li>TSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealing</li><li>TSVs: mechanical, thermal, and electrical behaviors</li><li>Thin-wafer strength measurement</li><li>Wafer thinning and thin-wafer handling</li><li>Microbumping, assembly, and reliability</li><li>Microbump electromigration</li><li>Transient liquid-phase bonding: C2C, C2W, and W2W</li><li>2.5D IC integration with interposers</li><li>3D IC integration with interposers</li><li>Thermal management of 3D IC integration</li><li>3D IC packaging</li></ul><p></p>