Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)

Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)

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<p>Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. <i>Logical Effort: Designing Fast CMOS Circuits</i> makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.<br><br><p>The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.<ul><li>Explains the method and how to apply it in two practically focused chapters.</li><li>Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.</li><li>Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.</li><li>Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.</li><li>Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.</li><li>Presents a complete derivation of the method-so you see how and why it works.</li></ul>