A Verilog HDL Primer

A Verilog HDL Primer

• Used Book in Good Condition

Written for new users. <P>Explains the language through simple examples. <P>Explains the syntax of language using commonly-used design terminology. <P>Explains the behavioral style, the dataflow style, and structural style in detail. <P>Concepts of delay and timing are clearly explained. <P>Testbench writing is made easier by providing a number of examples. <P>Many hardware modeling examples have also been provided to make this an excellent reference.